1. Field of the Invention
The present invention relates to a multiple input analog-to-digital conversion apparatus that converts multiple input analog signals such as two or more input analog signals to a digital signal, and a radio receiver using the same.
2. Description of the Related Art
A pipeline AD (analog-to-digital) converter is known as an AD converter realizing an analog-to-digital conversion at the high speed such as several hundred mega samples per second and a high accuracy more than 10 bits. The pipeline AD converter has a sub ADC (sub AD Converter) and MDAC (Multiplying DA Converter) in a plurality of conversion stages arranged in cascade, outputs MSB (Most Significant Bit) of a digital output signal from a first conversion stage and sequentially outputs lower order bits than the digital output signal on and after a second stage. Since the error of the sub ADC is corrected by a digital correction circuit, the precision of the MDAC having an operational amplifier, a capacitor and a MOS transistor switch is determined by precision of the pipe line AD converter.
The operational amplifier used for the pipeline AD converter needs a high-speed and a high accuracy for the AD converter to operate at high speed. Accordingly, the operational amplifier has a large power consumption in the pipeline AD converter which occupies a considerable ratio to the power consumption of the whole AD converter.
Because the pipe line AD converter outputs a higher order bit in the previous conversion stage, the precision required for each conversion stage is alleviated according to the order of decreasing stage. A method of decreasing an area and power consumption of the operational amplifier according to the order of decreasing stage by alleviating the precision required for each conversion stage is proposed by the non-patent literature 1 (D. W. Cline et al, IEEE J. Solid State Circuits, vol. 31, no. 3, pp. 294-303, Mar. 1996). This is a typical design technique of a lower consumption pipeline AD converter.
The non-patent literature 2 (B. M. Min et al, IEEE International Solid-State Circuit Conference Digest of Technical Papers pp. 324-325, 2003) provides a technique of reducing the number of necessary operational amplifiers to one-half by sharing an operational amplifier between adjacent conversion stages in a time sharing every half clock to realize further decreased power consumption of the pipeline AD converter. Such technique of sharing the operational amplifier in a time sharing utilizes that each of the adjacent conversion stages of the pipe line AD converter is in an active state every half clock.
The technique of sharing an operational amplifier between adjacent conversion stages in a time sharing cannot use an optimum operational amplifier on each conversion stage. In the case that an operational amplifier is shared between an N-th conversion stage and a (N+1)-th conversion stage in a time sharing, if the operational amplifier is optimized for the N-th conversion stage, the (N+1)-th conversion stage increases in power consumption and area more than necessary. Accordingly, according to the technique of the non-patent literature 1, the number of operational amplifiers decreases to one-half, but the power consumption is reduced only as much as 20-30%.
A plurality of AD converters are often used for subjecting to analog-to-digital conversion orthogonal modulation/demodulation signals or received signals from a plurality of receiving antennas in communications use such as a radio receiver. Accordingly, low power consumption of the AD converter is strongly required, and a solution is expected.
It is an object of the present invention to provide a multiple input analog-to-digital conversion apparatus which can realize lower power consumption than a conventional pipeline AD converter with respect to input analog signals of a plurality of channels.
It is another object of the present invention to provide a radio receiver of low power consumption by means of a multiple input analog-to-digital conversion apparatus.